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Google ASIC Subsystem Lead Silicon India, Karnataka, Bengaluru 954933742
09.06.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 8 years of subsystem design experience.
- Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation.
- Experience with RTL coding using Verilog or System verilog language.
Preferred qualifications:
- 15 years of RTL design and subsystem design experience.
- Domain knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains and Pin-muxing.
- Proficient with chip design flow and good understanding of cross-domain involving DV/DFT/Physical Design/Software.
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