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NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.
What you'll be doing:As a valued member of our team, you will take end-to-end ownership of DFX verification, pattern development, and silicon bring-up for a range of test features—including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations.
Work closely with various DFX teams, CAD, and methodology teams to improve the flows and processes.
In addition, you will help develop and deploy DFT methodologies for our next-generation products.
Be a part of innovation to strive to improve the quality of DFT methods.
You will also need to work with multi-functional teams to incorporate DFT features into the chip.
BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience.
You should be proficient in static timing analysis, ECO, ASIC/Logic Design Flow, HDL, and Digital logic design.
Experience in RTL and Gates verification, simulation, and silicon bring-up.
You need to be familiar with BIST architecture andJTAG/IEEE1149.1/IEEE1500/IEEE1687.
Strong DFT knowledge in Scan ATPG, compression techniques, and memory test.
Strong analytical and problem-solving skills with good scripting knowledge (either Perl/Python).
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