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The Role:
As Senior SERDES Design Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third-party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment.As a member of the Kuiper Silicon Development team, you will be responsible for the SERDES sub-system that is part of the digital-beamformer SOCs for the phased-array antennas, both for the Satellite products as well as the Customer Terminal ones.Export Control Requirement:Key job responsibilities
In this role you will:
· Support the internal Kuiper teams in the integration and optimization of the various high-speed SERDES links in phased-array antenna systems
· Simulate of 32Gbps SERDES IP for satellite communications
· Integrate 112Gbps PAM-4 SERDES IP into complex SoCs in advanced CMOS nodes
- Bachelor's degree in Electrical / Communications Engineering or related field
- 7+ years experience in SERDES design
- Experience with high-speed, low-power SERDES IP, especially the PHY layer
- Master’s / PhD degree in Electrical / Communications Engineering or related field
- 10+ years of hands on experience in high-speed (112Gbps), low power (<1pJ/bit) SERDES design and implementation
- Proven track record of bringing SERDES IP to production
- Familiarity with analyzing the impact of package and PCB on SERDES performance
- Familiarity with UCIe, PAM4 and other high-speed SERDES IP families
- Familiarity with FEC and DFE techniques
- Familiarity with Interlaken or other SERDES networking protocols
- Familiarity with SERDES ATE techniques (BIST, loopbacks, etc)
- Familiarity with IP deliverables and PD (LEF, LIB, timing closure, EMIR, etc.)
- Familiarity with SERDES AFE design
- Good communicator, Strong written and verbal skills
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