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Apple SoC Physical Design Engineer STA/Timing United States, California, Sunnyvale 230531500
08.06.2025
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In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.
- Minimum BS and 3+ years of relevant industry experience.
- Experience with large design STA and Timing Closure.
- Programming skills with Perl and TCL.
- Hands-on experience in STA.
- Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
- Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.
- Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
- Familiar with ECO techniques and implementation.
- Good communicator who can accurately describe issues and follow them through to completion.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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