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Google Chiplet Lead Silicon United States, California, Mountain View 173618512
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 8 years of experience in UCIe or Serial PHY Development.
- Experience in custom circuit design and simulation of Analog Mixed-Signal IP.
- Experience with SERDES IP integration such as PCIe, USB, D2D UCIe into SoC from feature definition to full design implementation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or a related field.
- Experience of Pre-silicon to Post-Silicon overall end to end execution of UCIe or high speed Serial PHY.
- Experience in Post-Silicon debug using the latest process technology nodes.
- Experience in developing multiple Analog Mixed-Signal IP.
- Excellent in statistical, data analysis, teamwork and communication skills.
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