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Nvidia Package Design Engineer 
United States, California 
237550043

Today
US, CA, Santa Clara
time type
Full time
posted on
Posted 10 Days Ago
job requisition id


What you'll be doing:

  • Your responsibilities will include defining the chip pad ring, substrate interconnect scheme, and lead the package layout design process for package test vehicles

  • The focus will be primarily on flip chip and 2.5D interposer based packages

  • Implementelectrical/mechanical/thermalstructures in test vehicles for effective package technology evaluations

  • Develop design flow for new package technologies

  • Collaborate with cross functional teams to incorporate various requirements in package designs

  • Work with off-shore fab and package assembly manufacturing partners to develop and implement package design rules


What we need to see:

  • BS in EE or ME (or equivalent experience)

  • 3+ years package design experience

  • Strong programming skills (Perl, Python, Tcl desired)

  • Working knowledge of Cadence Allegro Packaging Design (APD)

  • Experience in 2.5D packages

  • Strong problem solving skills

You will also be eligible for equity and .