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Perform full-chip EM/IR analysis, debug issues, provide solutions, and ensure signoff clean results. Conduct voltage-aware STA at both full-chip and block levels, review and resolve issues to achieve timing closure....
You will be responsible for macro level RTL to gds implementation and signoff. Work with Front-End teams to understand the design architecture to ensure optimal physical implementation. Execute critical physical...
Own the physical design and implementation of full-chip clock mesh networks, within the RTL-to-GDSII flow. Implement physical design tasks specifically tailored for clock mesh structures, including custom placement and routing....
Perform full-chip physical verification tasks, including DRC, LVS, ERC, and ANT checks, ensuring signoff-clean results. Debug and resolve physical verification issues at both block and chip levels, working closely with...
You will be responsible for macro level RTL to gds implementation and signoff. Work with Front-End teams to understand the design architecture to ensure optimal physical implementation. Execute physical design...
You will be responsible for macro level RTL to gds implementation and signoff. Work with Front-End teams to understand the design architecture to ensure optimal physical implementation. Execute physical design...
Participate and contribute to chip sensors architecture definition and discussions. Generate and verify different configurations of sensor to ASIC chip. Implement testbenches, run simulation and verification. Help define, evolve, and...
Perform full-chip EM/IR analysis, debug issues, provide solutions, and ensure signoff clean results. Conduct voltage-aware STA at both full-chip and block levels, review and resolve issues to achieve timing closure....
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