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ื”ืžืงื•ื ื‘ื• ื”ืžื•ืžื—ื™ื ื•ื”ื—ื‘ืจื•ืช ื”ื˜ื•ื‘ื•ืช ื‘ื™ื•ืชืจ ื ืคื’ืฉื™ื

ื“ืจื•ืฉื™ื Soc Logic Design Engineer Intermediate / Senior ื‘-ืื™ื ื˜ืœ ื‘-Canada, Vancouver

ืžืฆืื• ืืช ื”ื”ืชืืžื” ื”ืžื•ืฉืœืžืช ืขื‘ื•ืจื›ื ืขื ืืงืกืคื•ื™ื ื˜! ื—ืคืฉื• ื”ื–ื“ืžื ื•ื™ื•ืช ืขื‘ื•ื“ื” ื‘ืชื•ืจ Soc Logic Design Engineer Intermediate / Senior ื‘-Canada, Vancouver ื•ื”ืฆื˜ืจืคื• ืœืจืฉืช ื”ื—ื‘ืจื•ืช ื”ืžื•ื‘ื™ืœื•ืช ื‘ืชืขืฉื™ื™ืช ื”ื”ื™ื™ื˜ืง, ื›ืžื• Intel. ื”ื™ืจืฉืžื• ืขื›ืฉื™ื• ื•ืžืฆืื• ืืช ืขื‘ื•ื“ืช ื”ื—ืœื•ืžื•ืช ืฉืœืš ืขื ืืงืกืคื•ื™ื ื˜!
ื—ื‘ืจื” (1)
ืื•ืคื™ ื”ืžืฉืจื”
ืงื˜ื’ื•ืจื™ื•ืช ืชืคืงื™ื“
ืฉื ืชืคืงื™ื“ (1)
Canada
Vancouver
ื ืžืฆืื• 4 ืžืฉืจื•ืช
21.04.2025
I

Intel SoC Logic Design Engineer Junior Canada, British Columbia, Vancouver

Limitless High-tech career opportunities - Expoint

ืฉื™ืชื•ืฃ

ื”ืชื—ื‘ืจ/ื™ ื›ื“ื™ ืœื”ื’ื™ืฉ ืžื•ืขืžื“ื•ืช
ืชื™ืื•ืจ:
Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participate in the development of Architecture...
ืคืจื˜ื™ ื”ืžืฉืจื” ื”ืžืœืื™ื

ืžืฉืจื•ืช ื ื•ืกืคื•ืช ืฉื™ื›ื•ืœื•ืช ืœืขื ื™ื™ืŸย ืื•ืชืš

20.04.2025
I

Intel SoC Logic Design Engineer Intermediate / Senior Canada, British Columbia, Vancouver

Limitless High-tech career opportunities - Expoint

ืฉื™ืชื•ืฃ

ื”ืชื—ื‘ืจ/ื™ ื›ื“ื™ ืœื”ื’ื™ืฉ ืžื•ืขืžื“ื•ืช
ืชื™ืื•ืจ:
Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participate in the development of Architecture...
ืคืจื˜ื™ ื”ืžืฉืจื” ื”ืžืœืื™ื
14.04.2025
I

Intel Verification Engineer Intermediate/Senior Canada, British Columbia, Vancouver

Limitless High-tech career opportunities - Expoint

ืฉื™ืชื•ืฃ

ื”ืชื—ื‘ืจ/ื™ ื›ื“ื™ ืœื”ื’ื™ืฉ ืžื•ืขืžื“ื•ืช
ืชื™ืื•ืจ:
Develop and Optimize Verification Environments: Create and enhance verification plans, test benches, and test environments for different levels of System-on-Chip (SoC) design. Execute Simulations and Debug Issues: Run tests, simulations,...
ืคืจื˜ื™ ื”ืžืฉืจื” ื”ืžืœืื™ื
08.04.2025
I

Intel Verification Engineer Junior Canada, British Columbia, Vancouver

Limitless High-tech career opportunities - Expoint

ืฉื™ืชื•ืฃ

ื”ืชื—ื‘ืจ/ื™ ื›ื“ื™ ืœื”ื’ื™ืฉ ืžื•ืขืžื“ื•ืช
ืชื™ืื•ืจ:
Develop and Optimize Verification Environments: Create and enhance verification plans, test benches, and test environments for different levels of System-on-Chip (SoC) design. Execute Simulations and Debug Issues: Run tests, simulations,...
ืคืจื˜ื™ ื”ืžืฉืจื” ื”ืžืœืื™ื
ื‘ื•ืื• ืœืžืฆื•ื ืืช ืขื‘ื•ื“ืช ื”ื—ืœื•ืžื•ืช ืฉืœื›ื ื‘ื”ื™ื™ื˜ืง ืขื ืืงืกืคื•ื™ื ื˜. ื‘ืืžืฆืขื•ืช ื”ืคืœื˜ืคื•ืจืžื” ืฉืœื ื• ืชื•ื›ืœ ืœื—ืคืฉ ื‘ืงืœื•ืช ื”ื–ื“ืžื ื•ื™ื•ืช Soc Logic Design Engineer Intermediate / Senior ื‘ื—ื‘ืจืช Intel ื‘-Canada, Vancouver. ื‘ื™ืŸ ืื ืืชื ืžื—ืคืฉื™ื ืืชื’ืจ ื—ื“ืฉ ื•ื‘ื™ืŸ ืื ืืชื ืจื•ืฆื™ื ืœืขื‘ื•ื“ ืขื ืืจื’ื•ืŸ ืกืคืฆื™ืคื™ ื‘ืชืคืงื™ื“ ืžืกื•ื™ื, Expoint ืžืงืœื” ืขืœ ืžืฆื™ืืช ื”ืชืืžืช ื”ืขื‘ื•ื“ื” ื”ืžื•ืฉืœืžืช ืขื‘ื•ืจื›ื. ื”ืชื—ื‘ืจื• ืœื—ื‘ืจื•ืช ืžื•ื‘ื™ืœื•ืช ื‘ืื–ื•ืจ ืฉืœื›ื ืขื•ื“ ื”ื™ื•ื ื•ืงื“ืžื• ืืช ืงืจื™ื™ืจืช ื”ื”ื™ื™ื˜ืง ืฉืœื›ื! ื”ื™ืจืฉืžื• ื”ื™ื•ื ื•ืขืฉื• ืืช ื”ืฆืขื“ ื”ื‘ื ื‘ืžืกืข ื”ืงืจื™ื™ืจื” ืฉืœื›ื ื‘ืขื–ืจืช ืืงืกืคื•ื™ื ื˜.