Performs functional logic verification of an integrated Subsystem to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem verification plans, test benches, and the verification environment...
Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU...
Performs functional logic verification of an integrated Subsystem to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem verification plans, test benches, and the verification environment...