Iphone Product Design Engineering Project Manager Pd Epm jobs at Apple in United States, San Diego
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Company (1)
Job type
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Job title (1)
United States
State
San Diego
155 jobs found
08.06.2025
A
Apple SoC Physical Design Verification Engineer United States, California, San Diego
Minimum BS and 3+ years of relevant industry experience. Experience with physical verification flows: DRC/LVS/ANT/HVDRC signoff flows and/or full-chip integration methodology. Experience with ESD, macro placement design guidelines, digital/analog mixed...
BS + 10 years of relevant experience. Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering. Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR...
BS + 3 years of industry experience. Experience with ASIC DV. Knowledge of HVL methodology (UVM/OVM) with the most recent experience in UVM. Experience with formal verification. Experience track record...
Minimum Bachelor's degree. Experience with physical verification flows, DRC/LVS/ANT and/or layout integration methodology. Knowledge of RTL and GDS physical design flows. Scripting skills to debug flow related issues and make...
BS. Design and 3D CAD experience. Experience with multiple part assemblies. MS. 3+ years of industry experience. Experience with precision parts, consumer electronics or PCB design. Ability to generate detailed...
7+ years of construction/facilities management experience with a demonstrated focus in delivering and/or maintaining outstanding retail stores, workplaces, and/or critical environments. Proven ability to collaborate with internal and external stakeholders...
Minimum requirement of a bachelors degree. Strong understanding of digital logic design principles. Knowledge of scripting (like Shell, Python, and Perl). Knowledge of verification techniques including problem-solving, constrained random testing,...
Minimum BS and 3+ years of relevant industry experience. Experience with physical verification flows: DRC/LVS/ANT/HVDRC signoff flows and/or full-chip integration methodology. Experience with ESD, macro placement design guidelines, digital/analog mixed...
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